Past Self-alignment Work

Cherenack [1] developed both back-channel cut (Figure 1a) and back-channel passivated (Figure 1b) a-Si:H TFTs on clear plastic and developed two separate self-alignment steps:

· Self-alignment between the gate and the channel passivation

· Self-alignment between the gate and the S/D electrodes

These steps enabled the author to reduce the overlap between the S/D terminals and the gate from 15 µm down to 1 µm for back-channel passivated TFTs (Figure 1b). Figure 2a shows a close-up optical micrograph of one of the self-aligned TFT channel regions where the TFT channel length is 40µm. These back-channel passivated TFTs were fabricated at 250^oC on clear plastic using self-alignment between the gate, the channel passivation, and the S/D electrodes.

Electrical performance of self-aligned TFTs: the transfer characteristic of self-aligned back-channel passivated TFTs were measured to evaluate their electrical performance. The transfer characteristic of the TFT with a W/L of 80µm/40µm is shown in Figure 2b and the TFT performance parameters extracted from this figure are listed in Table 1. This TFT has state-of-the art performance characteristics, proving the the self-aligned process is compatible with the standard TFT fabrication process.

[1] K. H. Cherenack, Ph. D. Thesis, Princeton University, January 2009